Assert non-empty CLOCK_PORT exists

[kareefardi]

Description

Flow will continue normally. There will be warnings along the flow inside steps logs but I don't think that is sufficient.

Proposal

A CLOCK_PORT definition that doesn't exist should force the flow to quit.

[donn]

What about combinational IP? These do exist. Should we perhaps add a "COMBINATIONAL" variable to toggle this behavior?

[kareefardi]

For combinational IPs the designer can define an empty clock port variable or even chose not to define it at all. However, if one chooses to define a clock port (non-empty value) we should assert it's existence as a definition of an undefined port will cause issues in the flow and will not be considered a critical fail.

[donn]

I think an empty clock port is used in some corner cases, so I think this issue should be part of a wider discussion on clock and power domains in OpenLane.

[kareefardi]

The issue/proposal has nothing to do with empty clock port definitions