WARNING: 183 shift/reduce conflicts

Open shaos opened this issue 3 years ago • 1 comments

My project got this warning after successful MPW Precheck for https://platform.efabless.com/shuttles/MPW-8

STDOUT: {{SUCCESS}} All Checks Passed !!! STDERR: Generating LALR tables STDERR: WARNING: 183 shift/reduce conflicts

ID: 5565ebcf-2596-4d3d-8fd5-ca883cce2220 2022-12-28-TestAsyncTrimux 12/28/22 21:42:19 PST 12/28/22 21:46:13 PST succeeded MPW-Precheck-1.log

Dec 29 '22 16:12 shaos

That's an internal problem of PyVerilog and Verilog itself. I'm certain it will happen no matter the design you throw at the precheck. You can see the same warning in this issue. This repository could have code to catch and hide this warning though

Jan 02 '23 18:01 widlarizer