precheck does not pass consistency check for analog designs. part 2.

[d-m-bailey]

No analog design will pass precheck.

As indicated in #163

There is a change to the caravel/caravel-lite repo that will replace this file with a lef based extracted version that does have a user_analog_project_wrapper, but it is my belief that the further checks for vssa1_core, etc. connections will fail because these power nets are extracted differently (ie. mprj/vssa1, etc.)

Precheck currently fails due to unexpected power connections in spi/lvs/caravan.spice. precheck looks for vssa1_core, etc. but finds mprj/vssa1.

STDOUT: SUBMODULE HOOKS CHECK FAILED: The user power port vccd1 is not connected to the correct power domain in the top level netlist. It is connected to mprj/vccd1 but it should be connected to vccd1_core.

Either we change the layout so that these nets are labeled without becoming pins (@RTimothyEdwards says this should be possible https://github.com/efabless/mpw_precheck/pull/166#issuecomment-1325821105 ), re-extract and post the correct netlist to the caravel repo

OR

update the precheck program to look at the caravel/verilog/gl/caravan.v netlist instead (this is what #164 did).

I really don't think that the precheck should be checking against an extracted file that is not updated automatically. The verilog/gl/caravan.v file is used in the tapeout and is always current.