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How to use clock and wich pin number to use in design ?

Open Martoni opened this issue 1 year ago • 0 comments

As I can see in pcf files directory clock is usually connected on pin 37 :

$ cd openfpga_flow/tasks/SOFA_tasks/pcf_files
$ rg "clk"
counter.pcf
1:set_io clk gfpga_pad_io_soc_in[37]

adder.pcf
1:set_io clk gfpga_pad_io_soc_in[0]

$ rg "clock"
fifo.pcf
1:set_io clock gfpga_pad_io_soc_in[37]

two_digit_counter_ssg.pcf
1:set_io clock gfpga_pad_io_soc_in[37]

shift_reg.pcf
1:set_io clock gfpga_pad_io_soc_in[37]

(rg is for ripgrep)

But this clock is noted as the FPGA prog_clk in README.

It seems to stop a few ~100 ms after the eFPGA is configured.

I see a few fronts on the oscilloscope, then nothing.

Is there a configuration to keep running this prog_clk ?

Or should I use a different clock ?

Thanks

Martoni avatar Oct 06 '24 19:10 Martoni