make verify-mprj_por fails

[buzmeg]

PDK was installed using volare from earlier in the README.md

make verify-mprj_por
docker run -v /home/foo/efabless/caravel_user_project_analog:/home/foo/efabless/caravel_user_project_analog -v /home/foo/efabless/caravel_user_project_analog/pdk:/home/foo/efabless/caravel_user_project_analog/pdk \
                -v /home/foo/efabless/caravel_user_project_analog/caravel:/home/foo/efabless/caravel_user_project_analog/caravel \
                -e TARGET_PATH=/home/foo/efabless/caravel_user_project_analog -e PDK_ROOT=/home/foo/efabless/caravel_user_project_analog/pdk \
                -e CARAVEL_ROOT=/home/foo/efabless/caravel_user_project_analog/caravel \
                -u : efabless/dv_setup:latest \
                sh -c "cd /home/foo/efabless/caravel_user_project_analog/verilog/dv/mprj_por && export SIM=RTL && make"
/opt/riscv32i/bin/riscv32-unknown-elf-gcc -I /home/foo/efabless/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/foo/efabless/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/foo/efabless/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/opt/riscv32i/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex 
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -DEF_STYLE -I /home/foo/efabless/caravel_user_project_analog/pdk/ \
-I /home/foo/efabless/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/foo/efabless/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp 
/home/foo/efabless/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:30: Include file libs.ref/verilog/sky130_fd_io/sky130_fd_io.v not found
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
../../../verilog/rtl/example_por.v:57: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:68: error: Unknown module type: sky130_fd_sc_hvl__schmittbuf_1
../../../verilog/rtl/example_por.v:79: error: Unknown module type: sky130_fd_sc_hvl__lsbufhv2lv_1
7 error(s) during elaboration.
*** These modules were missing:
        sky130_fd_sc_hvl__lsbufhv2lv_1 referenced 2 times.
        sky130_fd_sc_hvl__schmittbuf_1 referenced 4 times.
***
make: *** [Makefile:51: mprj_por.vvp] Error 7
rm mprj_por.elf
make: *** [Makefile:61: verify-mprj_por] Error 2

[AidanMedcalf]

Fix: Edit top-level Makefile to pass $PDK to docker:

# Makefile line 60
$(DV_PATTERNS): verify-% : ./verilog/dv/%
    docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
                -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
                -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
                -e CARAVEL_ROOT=${CARAVEL_ROOT} -e PDK=${PDK} \
                -u $(id -u $$USER):$(id -g $$USER) efabless/dv_setup:latest \
                sh -c $(VERIFY_COMMAND)

After that it fails to include mgmt_core_wrapper.v, so there may be missing include paths.

[buzmeg]

I'm clearly not going to make this MPW, so I'm not that worried about getting this to pass right now and I assume the relevant folks are super busy with the deadline coming up Monday.

I'll be more aggressive about getting this fixed after Sept 19th or so after folks have put the MPW to bed. :)

Thanks.

[nkrackow]

I managed to get verify-mprj_por finishing by first doing https://github.com/efabless/caravel_user_project_analog/issues/29#issuecomment-1242429154 and then copying over mgmt_core_wrapper.v, mgmt_core.v and DFFRAM.v from https://github.com/efabless/caravel_mgmt_soc_litex/tree/main/verilog/rtl and adding

	`include "mgmt_core.v"
	`include "DFFRAM.v" 

to caravan_netlist.v in lines 92, 93. Now I can look at the vcd traces from the sim. :)

I guess this has something to do with switching over to litex mgmt core and stuff hasn't been updated in the analog user project. I just started playing around with caravel and the open pdk so I don't feel qualified to dig in and properly fix this but I hope this helps.

[jeffdi]

PR ready for merge