Running tests on Caravel's user_project_example does not work with the latest iVerilog release

[ellen-wood]

If using the latest iverilog (as distributed with the OSS_CAD_Suite Icarus Verilog version 13.0), the test for user_project_example does not work. It works fine with Icarus Verilog version 10.3 (stable).

Running the test: from directory caravel_user_project/verilog/dv/io_ports running make now yields the following error:

/root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:74: error: 'io_in' has already been declared in this scope. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:64: : It was declared here as a net. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:75: error: 'io_out' has already been declared in this scope. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:65: : It was declared here as a net. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:76: error: 'io_oeb' has already been declared in this scope. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:66: : It was declared here as a net. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:138: error: 'ready' has already been declared in this scope. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:134: : It was declared here as a net. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:139: error: 'count' has already been declared in this scope. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:136: : It was declared here as a net. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:140: error: 'rdata' has already been declared in this scope. /root/eda//caravel_user_project/verilog/rtl/user_proj_example.v:135: : It was declared here as a net.

It seems the way to fix it is to change the user_project_example.v file from:

    // IOs
    input  [15:0] io_in,
    output [15:0] io_out,
    output [15:0] io_oeb,

    // IRQ
    output [2:0] irq
);
    wire clk;
    wire rst;

    wire [15:0] io_in;
    wire [15:0] io_out;
    wire [15:0] io_oeb;

to

    // IOs
    input wire [15:0] io_in,
    output wire [15:0] io_out,
    output wire [15:0] io_oeb,

    // IRQ
    output [2:0] irq
);
    wire clk;
    wire rst;

and similar on lines 130 - 140:

    output reg ready,
    output reg [15:0] rdata,
    output reg [15:0] count
);

and delete the duplicate declarations (138 - 140) in the body of the module.

Maybe there is a way to use the old iverilog to read this instead?

[ellen-wood]

Oh I've just been informed this is a known issue, apologies!

[fkwilken]

Did you find a way to get past it? Or just implement those changes on your fork