mpw-two-c to mpw-5b tags use picorv32 instead of vexRISC for simulation

[mguthaus]

If you look at this tag, for example:

https://github.com/efabless/caravel_user_project/tree/mpw-two-c

It has a submodule link to caravel @ 13f2590 which uses the picorv32 CPU instead of the vexRISC. By default, the Makefile uses the submodule. So... all projects were simulating with the wrong RISC core. It was updated in tag mpw-5b.

While this may not result in a silicon problem, it does result in issues with the compiler toolchain that were used to create tests for MPW2-5 by all users. I'm still digging into how to get around this and what the implications are but it seems to be quite sweeping.

(I'm trying to resimulate my MPW-2 project and ran into this while debugging...)