caravel_mgmt_soc_litex
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efabless
https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
The declaration of regs as ``` reg x = 1'b1; ``` such as in https://github.com/efabless/caravel_mgmt_soc_litex/blob/3222bd57445eb6e734f010b9bed369b53c6066fe/verilog/rtl/mgmt_core.v#L150 isn't supported in ASIC synthesis. This is equivalent to ``` reg mgmtsoc_vexriscv; initial mgmtsoc_vexriscv =...
Please remove this branch after merging. fix for https://github.com/efabless/caravel_user_project/issues/347
Added an initialization loop to the SPI flash emulation module, which prevents mysterious errors caused by prefetching memory past the end of a program, resulting in undefined values propagating through...
After working on an AES accelerator to be integrated in the user_project_wrapper in caravel, we noticed that the CPU takes around 9000 clock cycles to do a single read or...
https://github.com/efabless/caravel_mgmt_soc_litex/blob/43d0ce33d331ee73d9dcebe197c6ce4da5909ecc/verilog/rtl/mgmt_core.v#L1774C31-L1774C31 This like appears to connect the SPI master controller `Data Out Output Enable (active low)` to the **INVERTED** signal of the `SPI CS (active low)` as a signal source....
This PR updates the litex mgmt core and locks the submodules the core is generated from. The list of changes is as follows: * Added dependencies as Git submodules for...
The simulation with the `riscV (VexRISC) ` cpu is way slower than `swift2`. `Swift2 `is faster more than 4 times. This may be because `riscV (VexRISC) `cpu doesn't have cache...
Same as https://github.com/efabless/caravel/pull/419, but for mgmt_soc_litex repo
