efabless
mgmt_protect block was synthesized incorrectly with buffers on inputs
This is probably my fault for saying once that all inputs should be buffered in openlane without considering that there are specific exceptions to this. The management protection circuitry depends on having all inputs from the user project area ANDed with the input enable signal. This allows the management SoC control which inputs are active, and allows all unused inputs to be left floating. However, that only works correctly if the input gate is an AND (or in this case, actually a NAND), so that if one input of the gate is grounded, then the other input is a don't care and can be left physically floating. By putting a buffer in front of the AND gate, the buffer can draw crowbar current if the input is floating.
It is also unclear to me why openlane uses "clkbuf" buffers for input buffering. There is no particular need for an oversized balanced buffer just to provide input buffering (other than buffering a clock network).
Solution: All user-side inputs to the management protect block (mgmt_protect) should be exempted from being buffered by the openlane scripts. That includes: la_data_out_core (128 signals), user_irq_core (3 signals), mprj_dat_i_user, and mprj_ack_i_user (one signal each).
so this is in mpw2/3/4? What are the repercussions? If the input is floating then the chip may draw too much current and fail to run?
@mattvenn : Yes, this appears to have been applied to MPW2/3/4. The repercussions is generally that the inputs in question will dump current if the value is mid-range between power and ground, and there being several hundred of those signals, it could possibly generate enough current to pull the power supply down. In practice, the floating inputs will tend to drift toward one of the power rails, and dumping a lot of instantaneous current at that circuit probably won't affect operation of the management CPU, which is pretty far away.
I should also add here that the inputs user_gpio_oeb and user_gpio_out on the gpio_control_block module need to be handled in the same way, with no buffer on the input, as these inputs have been designed similarly to those on the management protect block, with an AND gate (or similar) allowing the signal to remain unconnected (floating) as long as the GPIO control block has the management enable bit set.
@shalan : These are the signals that need to be left unbuffered:
(1) For cell mgmt_protect:
la_data_out_core
mprj_dat_i_user
mprj_ack_i_user
user_irq_core
(2) For cell gpio_control_block:
user_gpio_out
user_gpio_oeb
Addressed by virtue of changing the MGMT protect block outputs to active low on power down for core instead of tristate.
