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Caravel ORCX check of corners extraction at top level vs commercial tool
We noticed in timing review of chip level post layout STA that nom to max and nom to min parasitic delays seem to be changing by only about 3-5% where the block level numbers seem to change more than 10%. The request is to check the ominal version of a fullchip mnet parasitic set vs a commercial tool.
Done for housekeeping (shows errors < 10ps) Need to be done for the management core wrapper (larger wires/distances)
Review data from Kareem before closing this.