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Hi @wip-abramson , I did not find any answer to this. Searching in [email protected] public mail archive (https://lists.w3.org/Archives/Public/public-credentials/ ), I failed to find anything related. Are you participating in the...

@bunnie this whole take on a **compressed instructions first** RISC-V CPU might be of interest to you, https://betrusted.io/ , Xous, and maybe even Precursor.

Would it be too much work to switch to VHDL-2019 to allow for special-casing these problematic constructs (i.e. macro-like preprocessing)? There seems to be even a standalone Python app adding...

Sounds encouraging when the author - you - says that :wink:. Do you plan to rewrite it at some point?

I might know of some people who could have the cycles to rewrite this to Verilog or do the necessary patching for a first tape out (or at least first...

@dodotronix someone from your circles, colleagues etc. could chime in with their experience and thoughts.

Just saw GSOC ideas regarding chips and thought there might be (or perhaps not) an option to get some students to make their hands dirty with minimax or related: https://github.com/chipsalliance/ideas...

It seems the patch did not make it into master yet. Any plans to do so? Thanks!

Thanks for clarification. Do you think it would make sense to implement such "deferred" incremental allocation? Or is it out of scope for this lib?

It should not add basically any overhead. Nim uses only thread-local variables everywhere and Nim's peformance is equal to C in single-threaded.