Oleg Burdaev
Oleg Burdaev
@aminixduser Different operator-modulator relations could speed up the whole process if the operator loop is rolled out. But this will cost about 1.5K of the code size :(
Yes non-inline function will make ip changes and slow down all. One more option is to roll out matrix per algorithm. But again it would be 32 compare-branch construct per...
Feedback could be moved from if-then-else to simple if-then so it will be the same bit test and conditional 2 adds with no branching. But the main matrix still needs...
@aminixduser Looks like I found the way: if ((int8_t)(algorithm[i]
@aminixduser I was just thinking about this but in the different way. Since by design carrier always have a greater number, we have actually 15 possible modulations per sample, instead...
With the new timings, the (best case with no contention) ``` 1c lsls r1, r0, #30 1c itt mi 2c ldrmi.w r1, [r4, #680] ; 0x2a8 1c addmi r3, r3,...
That will be just like at least on OP modulation can be skipped in the worst case. I currently implementer variant 4 and it will do the same in case...
@aminixduser implemented in 63a25f4 though since not all the loop in the asm, some overhead introduced by compiler - 1 or 2 movs (modw0 preserved/restored for unknown reason) - 1...
> Nice work, that is a good improvement! > I had another idea pop in my head. Why not use the MOD1_MASK bit, change its meaning to "NO_MOD and NO_FB"...
@aminixduser Have a better idea. Imagine we have all opval and modw in registers. It wil be just ``` 5c tbb 1c lsls 1c it 1c addmi ... ``` 5....