Richard Lin

Related: #14, a more general case of driving clock signals within the testbench and supporting true multiclock designs. But, if your use case doesn't need the full power of multiple...

I've heard of people playing with this for various protocols, but I'm not aware of any released or example/documentation-grade code. One potential issue with a testing library is that it...

I agree that this reusable library ultimately this is the dream and goal of chiseltest, but also realistically, there's a lot of groundwork in standardizing chisel libraries that are necessary...

Strange. I don't know what's going on but: - As architected, chiseltest shouldn't actually be running anything in parallel. Chiseltest spawns threads only to track execution context, but threads are...

So today during chisel-dev, @jackkoenig (I think?) linked [a page on fibers in Cats Effect](https://typelevel.org/blog/2021/02/21/fibers-fast-mkay.html). The page doesn't talk too much about API or implementation, but the short of it...

I think with the hybrid option, it just means the scheduler needs to handle both threads and fibers, where fibers wouldn't incur a thread switch. I'm more concerned about the...

Cool! So giving it a bit of though, there's more than one option for a memory access API: - As you have in your PR, it would be `mem.poke(i, value)`...

About partial Bundle literal pokes: mainly an API design consideration, instead of a can-we-do-it issue (which we can, as demonstrated with `pokePartial`). The idea is that the common API is...

We discussed this at the dev meeting today: - **In general, there are no guarantees on memory structure from FIRRTL transforms.** The current behavior, defined by a transform, is to...

Yes, I think you're correct. I'm not completely sure on naming guarantees, but in general it's probably best to use a "feedback" API (eg, a rename map from FIRRTL -...