Will Dietz

icon indicating a website link https://wdtz.org

icon company @SiFive icon location Will Dietz at @SiFive. personal: @dtzWill

Results 55 issues of Will Dietz

Layers not emitted when used as colors of probes with separate elaboration

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** 1. Checkout this commit of Chisel (small change to test to demonstrate issue): https://github.com/chipsalliance/chisel/commit/49325496999148dc3fe48c093a16811134715cfb 2. `testOnly chiselTests.experimental.hierarchy.SeparateElaborationSpec`...

Probe color should be checked for read

**Type of issue**: Bug Report scala-cli demonstration: ```scala //> using repository "sonatype-s01:snapshots" //> using scala "2.13.14" //> using dep "org.chipsalliance::chisel:7.0.0-M2+76-ecda00a5-SNAPSHOT" //> using plugin "org.chipsalliance:::chisel-plugin:7.0.0-M2+76-ecda00a5-SNAPSHOT" //> using options "-unchecked", "-deprecation", "-language:reflectiveCalls",...

bug

[FIRRTL] Layers and Analog

Consider: ```firrtl FIRRTL version 4.0.0 circuit Foo : layer L, bind : extmodule Bar : input a : Analog public module Foo : input a : Analog layerblock L: inst...

FIRRTL

[FIRRTL] memory parsing support for combined port declarations - document/spec, comma-separate?

Consider: ```firrtl FIRRTL version 4.0.0 circuit Foo: public module Foo: mem memory: data-type => UInt depth => 8 reader => foo bar baz read-latency => 0 write-latency => 1 read-under-write...

FIRRTL

[FIRRTL] memory parsing crashes on unexpected order of "fields"

Consider: ```firrtl FIRRTL version 4.0.0 circuit Foo: public module Foo: mem memory: depth => 8 reader => r read-latency => 0 write-latency => 1 read-under-write => undefined data-type => UInt...

FIRRTL