Will Dietz
Will Dietz
Example FIRRTL: ``` FIRRTL version 3.3.0 circuit Bar : module Foo : input clock : Clock output clockProbe_bore : RWProbe define clockProbe_bore = rwprobe(clock) module Bar : input clock :...
**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** Consider these tests: https://github.com/dtzSiFive/chisel3/commit/d8a3f1213c32a9e69fd6e15eaf4c9030ce2235fb . Steps to reproduce are to checkout that branch / apply that commit...
Consider this MLIR example: ``` module { firrtl.circuit "OMIRField" { firrtl.module @OMIRField(in %x_b: !firrtl.uint, out %y_b: !firrtl.uint) { %n_b = firrtl.node sym @omir_sym %x_b : !firrtl.uint firrtl.strictconnect %y_b, %n_b :...
When parsing FIRRTL >= 4.0.0, check and reject use of abstract reset on extmodule's. https://github.com/chipsalliance/firrtl-spec/pull/181 Previously implemented as part of #6731, but used in practice so deferred. Let's revisit now.
As of #6875, port directions as now encoded with a DenseArray. In the rationale we mention we still encode with IntegerAttr, this should be updated to reflect what's been learned...
Example: ```firrtl FIRRTL version 4.0.0 circuit Cyclic: public module Cyclic: inst f of Foo module Foo: inst c of Cyclic ``` Infer Resets presently overflows its stack recursing. Skipping that,...
WIP, tests and careful self-review still need to be done. Posting for visibility. Builds on #7137 (this is all unreachable after that PR).
Consider: ``` FIRRTL version 4.0.0 circuit ConstAlias: type X = { a: const UInt } public module ConstAlias: input x : X output y : X connect y, x ```...
* Verify specified symbols resolve for extmodule * Verify specified symbols resolve to LayerOp's * Verify public modules don't enable circuit-disabled layers. (SpecializeLayers will delete if so)
Instances and anything else with side-effects cannot be sunk into a layer without changing the behavior of the base program. Consider this FIRRTL input: ```firrtl FIRRTL version 4.0.0 circuit DUT...