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[BUG] naflexvit_so400m_patch16_siglip has undocumented different default pos_embed_interp_mode of "bicubic" instead of "bilinear"

Cosine similarities of the intermediate hidden states on a test image (pre-resized to 384x384, also made sure both are running on 576 seqlen) are roughly 0.985-0.99, and the pooled outputs...

nvidia-smi on WSL side causes NVRM driver non-paged pool memory leak

[WslLogs-2025-03-29_17-13-26.zip](https://github.com/user-attachments/files/19523013/WslLogs-2025-03-29_17-13-26.zip)

nvidia-smi on WSL side causes NVRM driver non-paged pool memory leak

Another possible instance of this bug is happening whenever I initialize a CUDA context using PyTorch. Simply loading an interactive Python shell and using: ```py >>> import torch >>> x...