dreamflyings
dreamflyings
1. If spinalsystemverilog is used, Verilog is generated after mergertlsource instead of SystemVerilog 2. If spinalconfig is configured as onefilepercomponent, and only report blackboxesSourcesPaths. Add, but without mergertlsource, the files...
When I was writing test code, I found an interesting question. // todo vtype_t is a bundle val rst = ClockDomain.current.reset.pull() val tmp = (vtype_t().getZero).setAsReg().allowOverride // todo It's work, tmp...
Hello ! When I was rewriting the SV code, I found some unexplainable phenomena. The correct and runnable code is on the next line of todo. And the variable result_d...
make verilog/make emu出现如下问题： ``` Connection:[DISPLAY_LOG_ENABLE] type:[func] source location:[SimTop] sink location:[AXI4RAM_1] Connection:[logTimestamp] type:[func] source location:[SimTop] sink location:[AXI4RAM_1] Connection:[XSPERF_CLEAN] type:[func] source location:[SimTop] sink location:[L2Prefetcher] Connection:[XSPERF_DUMP] type:[func] source location:[SimTop] sink location:[L2Prefetcher] [deprecated] ListBuffer.scala:153...
Which branch can run on the vcu118 board? Thanks!
Are there any settings that can solve this problem? [error] (run-main-0) java.lang.OutOfMemoryError: GC overhead limit exceeded [error] java.lang.OutOfMemoryError: GC overhead limit exceeded [error] at java.base/java.util.Arrays.copyOf(Arrays.java:3689) [error] at java.base/java.util.ArrayList.grow(ArrayList.java:237) [error] at...
Hi~ SpinalHDL language itself has good generalization and maintainability, But the quality of the verilog code it generates is not high, the maintainability is poor, and it is difficult to...
Dear Dolu1990 The Nax project is really great! Its software architecture is very helpful for learning and research, and it also has great application prospects in engineering implementation. I sincerely...
The current usage is as follows: ```scala NaxScope.create(xlen = 32) val frame = new MyPlugins(plugins).framework ``` Can the parameter configuration and auto-negotiation mechanism be generalized and independent. like this: [https://github.com/chipsalliance/cde/blob/master/cde/src/chipsalliance/rocketchip/config.scala](url)...
Hello! While writing multi-clock domain code, I discovered that referencing clock domains can cause changes in the interface names of identical components. SpinalHDL mistakenly treats these components as different modules...