dreamflyings

Another solution to the second phenomenon is to set be to Vec.

> Hi, > > The code sample, copy pasted, has some chisel stuff in it (Wire), can you send a fully SpinalHDL compilable one ? > > Then about the...

@Dolu1990 Thank you very much! Not only replied to the points of concern in detail, but also quickly fixed the BUG. I understand the usage of := and `\=`. However,...

@dxsm try this `class TestBitsAssignTop(width: BitCount) extends Component{` ` val myBits_32 = B(32 bits, default -> True) ` ` val myBits_8bits = Bits(8 bits) ` ` myBits_8bits := myBits_32( 7...

> Hi, Do you have a simple self contained example to reproduce ? Thank you! Examples of recurrence are as follows: ```scala import spinal.core._ object MergeRTL0 extends App{ val report...

> Hi, Do you have a simple self contained example to reproduce ? By the way, how can I use VCS simulator to simulate according to SV instead of Verilog....

@Dolu1990 Hello, Dolu1990 ,thank you very much for your reply, thank you for your outstanding contribution to spinalHDL. Thank you also for writing such an incredible software framework like Vex....

> Hi, > > Here are my thought, note that it doesn't mean i do not agree, it can mean i would need some practical explanation of the cases which...

> One thing, if you have two equivalent module generated, SpinalHDL will only emit the verilog of one and reuse it, but for it to work, your scala/spinalHDL elaboration need...

> Hi, > > Thanks for the examples ^^ > > About 1) > > Got it reduce by 45% by allowing resize node to simplify themself when useless. I...