building for ecp5

[Oscilllator]

I can't get things to compile for the ecp5 architecture.

I am using a recent (last week or so) build of oss-cad-suite to do the synthesis. synthesising fails with the following error message:

nextpnr-ecp5  --ignore-loops --um5g-85k --package CABGA381 --lpf ecp5-evn.lpf --json top_ecp5.json --textcfg top_ecp5.txtcfg


Info: Logic utilisation before packing:
Info:     Total LUT4s:       251/83640     0%
Info:         logic LUTs:    215/83640     0%
Info:         carry LUTs:     36/83640     0%
Info:           RAM LUTs:      0/10455     0%
Info:          RAMW LUTs:      0/20910     0%

Info:      Total DFFs:        92/83640     0%

Info: Packing IOs..
Info: pin 'TX$tr_io' constrained to Bel 'X0/Y92/PIOA'.
Info: pin 'RX$tr_io' constrained to Bel 'X0/Y56/PIOA'.
Info: pin 'J1_9$tr_io' constrained to Bel 'X0/Y83/PIOC'.
Info: pin 'J1_8$tr_io' constrained to Bel 'X0/Y86/PIOA'.
Info: pin 'J1_7$tr_io' constrained to Bel 'X0/Y56/PIOB'.
Info: pin 'J1_6$tr_io' constrained to Bel 'X0/Y77/PIOA'.
Info: pin 'J1_5$tr_io' constrained to Bel 'X0/Y86/PIOC'.
Info: pin 'J1_4$tr_io' constrained to Bel 'X0/Y89/PIOA'.
Info: pin 'J1_3$tr_io' constrained to Bel 'X0/Y86/PIOD'.
Info: pin 'J1_10$tr_io' constrained to Bel 'X0/Y83/PIOA'.
Info: pin 'CLK$tr_io' constrained to Bel 'X63/Y0/PIOA'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     63 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net CLK$TRELLIS_IO_IN to global network
Info:     promoting clock net J1_8$TRELLIS_IO_OUT to global network
Info: Checksum: 0x72c6a254

Info: Annotating ports with timing budgets for target frequency 12.00 MHz
ERROR: cell type 'TRELLIS_SLICE' is unsupported (instantiated as 'ringosci_slow.delayline[7].chain_lut')
0 warnings, 1 error
Makefile:106: recipe for target 'top_ecp5.txtcfg' failed
make: *** [top_ecp5.txtcfg] Error 255

This is a pity as I was hoping to use this repository as an example of how to use the TRELLIS_SLICE primitive to build a ring oscillator after reading: https://github.com/DurandA/verilog-buildingblocks/issues/1

I'll update this issue with a solution if I manage to find one...

[dpiegdon]

Hi, I haven't done anything with FPGAs for about a year or so. I've had trouble reactivating my toolchain, so I wasn't able to reproduce this yet. Any news from your side?

[DurandA]

Hi @Oscilllator and @dpiegdon

I also stopped playing with FPGAs. I do not remember having to enable anything specific in order to use a TRELLIS_SLICE. I would suggest to open an issue on YosysHQ/prjtrellis.

[davidar]

Support for TRELLIS_SLICE was removed from yosys/nextpnr: https://github.com/YosysHQ/nextpnr/issues/1131

I've tried replacing it with LUT4 (https://github.com/davidar/verilog-buildingblocks/commit/589a4acc3e220d263081ff94057940f1b0fdc75e) but I'm still getting build errors due to timing analysis getting confused by the ring:

Info:     loop 2207:
Info:         M_frame_display.rng9.m_osc[9].r2.delayline[0].chain_lut.A (M_frame_display.rng9.m_osc[9].r2.chain_wire[0])
Info:         M_frame_display.rng9.m_osc[9].r2.delayline[0].chain_lut.F (M_frame_display.rng9.m_osc[9].s2)
Info:         M_frame_display.rng9.m_osc[9].r2.delayline[1].chain_lut.A (M_frame_display.rng9.m_osc[9].s2)
Info:         M_frame_display.rng9.m_osc[9].r2.delayline[1].chain_lut.F (M_frame_display.rng9.m_osc[9].r2.chain_wire[0])
Info:     loop 2208:
Info:         M_frame_display.rng9.m_osc[9].r3.delayline[0].chain_lut.A (M_frame_display.rng9.m_osc[9].r3.chain_wire[0])
Info:         M_frame_display.rng9.m_osc[9].r3.delayline[0].chain_lut.F (M_frame_display.rng9.m_osc[9].s3)
Info:         M_frame_display.rng9.m_osc[9].r3.delayline[1].chain_lut.A (M_frame_display.rng9.m_osc[9].s3)
Info:         M_frame_display.rng9.m_osc[9].r3.delayline[1].chain_lut.F (M_frame_display.rng9.m_osc[9].r3.chain_wire[0])
ERROR: Timing analysis failed due to combinational loops.
0 warnings, 1 error