Jit: Flush registers used in memory breakpoint conditions

[JosJuice]

Aims to fix https://bugs.dolphin-emu.org/issues/13686.

I'm using a less efficient approach for Jit64 than for JitArm64. In JitArm64, I'm flushing in the slow access code, but in Jit64, I'm flushing before the split between the slow access code and the fast access code, because Jit64 doesn't keep register mappings around for when it's time to emit the slow access code. But the flushing code is only emitted when there are memory breakpoints with conditions, so I'd say that this is a performance loss we can live with.

[Amphitryon0]

Confirmed it fixes the issue in Jit64.

[JosJuice]

Judging from the names I would guess that all of the instructions that read or write to memory are implemented in *_LoadStore.cpp, *_LoadStoreFloating.cpp, and *_LoadStorePaired.cpp. Is that right?

Yes.

Is dcbz the only dcb* instruction that can write to memory, or if not is there another reason the other dcb* instructions don't need to flush registers?

If I didn't miss anything when looking through those instructions just now, the following dcb* instructions can write to memory:

• dcbz
• dcbz_l (but this one isn't implemented in the JIT, so it falls back to the interpreter, which causes all registers to be flushed)
• dcbst (but only if accurate cache emulation is enabled, and having it enabled makes the JIT fall back to the interpreter for this instruction, which causes all registers to be flushed)

So I do believe dcbz is the only one that needs flushing in the JIT.