Vectorization + Sequence Emit

[mbstrange2]

Joey,

I was hoping you could help me out with your autovectorization and make it generate single width addresses for items internally represented as multiple ports. For instance, the agg and sram interfaces are still represented as individual data units with address strides to reflect that (strides of 4 on all 4 read ports of agg), but we control the address at the word level. This could be reduced to a single read port with stride 1.

Additionally, I was hoping you could have some code to emit the application sequence to aid in automated testing - the form of the sequence needn't be any more complicated than a csv with the following format -

cycle, data_in, data_out, valid_out 0, 0, 0, 0 1, 1, 0, 0 1, 1, 2, 1

[joyliu37]

Address the sram word level access pattern in this commit. https://github.com/dillonhuff/clockwork/commit/2fae9e60cd1992d916bae8d442599e09cdae8872 You can pull the most up-to-date lower_buffer branch. I will try to get you the sequence for you.