[SKiDL BUG]generate_svg is not working properly in some contexts

[selimbayhan]

Describe the bug generate_svg is not working properly in some contexts

To Reproduce Run the below code

from skidl import *


esp32 = Part('RF_Module', 'ESP32-WROOM-32', footprint='ESP32-WROOM-32')


power_meter = Part('Sensor_Energy', 'ATM90E26-YU', footprint='SSOP-28')



ldo_regulator = Part('Regulator_Linear', 'LM1117MP-3.3', footprint='SOT-223')
vin_cap = Part('Device', 'C', value='10uF', footprint='C_0805')
vout_cap = Part('Device', 'C', value='10uF', footprint='C_0805')


relay = Part('Relay', 'G6E', footprint='G6E-SMD')
relay_driver = Part('Transistor_FET', '2N7002', footprint='SOT-23')


shunt_resistor = Part('Device', 'R', value='0.01', footprint='R_1206')


decoupling_cap1 = Part('Device', 'C', value='0.1uF', footprint='C_0805')
decoupling_cap2 = Part('Device', 'C', value='10uF', footprint='C_0805')


program_header = Part('Connector', 'Conn_01x06_Pin', footprint='Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical')
program_header[1] += esp32['GND']       # Ground
program_header[2] += esp32['VDD']       # 3.3V power
program_header[3] += esp32['TXD0/IO1']  # ESP32 TX (connect to RX on programmer)
program_header[4] += esp32['RXD0/IO3']  # ESP32 RX (connect to TX on programmer)
program_header[5] += esp32['EN']        # Enable pin
program_header[6] += esp32['IO0']       # IO0 (for boot mode)


esp32['VDD'] += ldo_regulator['VO']
esp32['GND'] += ldo_regulator['GND']


esp32['TXD0/IO1'] += power_meter['SDI/URX']
esp32['RXD0/IO3'] += power_meter['SDO/UTX']


power_meter['I1P'] += shunt_resistor[1]
power_meter['I1N'] += shunt_resistor[2]

relay[1] += relay_driver['D']  # Assume pin 1 is COIL+
relay[7] += ldo_regulator['GND']  # Assume pin 7 is COIL-


ac_connector = Part('Connector', 'Conn_01x02_Pin', footprint='PinHeader_1x02_P2.54mm_Vertical')
relay[6] += ac_connector[1]  # Assume pin 6 is COM
relay[10] += ac_connector[2]  # Assume pin 10 is NO


ldo_regulator['VI'] += vin_cap[1]
ldo_regulator['VO'] += vout_cap[1]
vin_cap[2] += ldo_regulator['GND']
vout_cap[2] += ldo_regulator['GND']


esp32['VDD'] += decoupling_cap1[1]
decoupling_cap1[2] += ldo_regulator['GND']
esp32['VDD'] += decoupling_cap2[1]
decoupling_cap2[2] += ldo_regulator['GND']


generate_svg()

got the following error:

Traceback (most recent call last): File "D:\PycharmProjects\edagenius\circuit_a5ff30ff-2313-45a2-8b7a-bda99cf68396.py", line 80, in generate_svg() File "D:\PycharmProjects\edagenius\venv\lib\site-packages\skidl\circuit.py", line 1024, in generate_svg self.generate_netlistsvg_skin( File "D:\PycharmProjects\edagenius\venv\lib\site-packages\skidl\circuit.py", line 721, in generate_netlistsvg_skin part_svg[name] = part.generate_svg_component( File "D:\PycharmProjects\edagenius\venv\lib\site-packages\skidl\part.py", line 1052, in generate_svg_component return tool_modules[tool].gen_svg_comp(self, symtx=symtx, net_stubs=net_stubs) File "D:\PycharmProjects\edagenius\venv\lib\site-packages\skidl\tools\kicad8\gen_svg.py", line 466, in gen_svg_comp _, bb = draw_cmd_to_svg(cmd, tx, part, net_stubs, max_stub_len) File "D:\PycharmProjects\edagenius\venv\lib\site-packages\skidl\tools\kicad8\gen_svg.py", line 295, in draw_cmd_to_svg shape["effects"].get("justify", shape.get("justify", "left")).lower() AttributeError: 'list' object has no attribute 'lower'

Expected behavior Generate the SVG

Desktop (please complete the following information):

• OS [type & version] windows
• Python version Python 3.9
• SKiDL version [e.g. 22] 1.2.3
• Kicad 8

[tari]

I'm seeing this as well, using the symbol Memory_RAM:CY62256-70PC as provided with Kicad 8. By inspection, shape["effects"]["justify"] for this symbol is [Symbol('left'), Symbol('bottom')] where those correspond to the horizontal and vertical justification for the symbol value text when viewed in Kicad's symbol editor.