add oscillator clock definition

[jg1uaa]

Oscillator clock is assumed as 32MHz (internal or external), but this makes difficult to support the board that has 16MHz external xtal; MassDuino UNO R3.

Add F_OSC, oscillator clock definition. To determine clock divisior, use F_OSC and F_CPU value.

Also, problem with using external clock (bootloader) and internal clock (sketch) is fixed.

[LaZsolt]

There are two type of WAVGAT boards has 12 MHz external crystal:

WVACAT uno style	WAVGAT nano style

I think we can support 12 MHz external clock also.

[LaZsolt]

I think we can support 12 MHz external clock also.

Perhaps in a new pull request.

[jg1uaa]

This PR also help these boards. @LaZsolt is there any (official) BSP for these board, and needs special bootloader?

[LaZsolt]

is there any (official) BSP for these board, and needs special bootloader?

I don't know. I ordered one form Aliexpress for my experiments. The seller's link points to the same WAVGAT package than 16 MHz version. I think not needs a special bootloader, only a new external clock options in the boards.txt I'm just trying to write how to select 12 or 16 MHz external crystal.

The buyers has a lot of complain about the wrong clock speed selection. Eg: And if you like just Nano, this is very slow. This is working at 4MHz not 16.

[LaZsolt]

My idea to modification of boards.txt is:

# Clock source
328.menu.clock_source.internal=Internal 32 MHz
328.menu.clock_source.internal.build.clock_source=1
328.menu.clock_source.internal.build.f_osc=32000000L
328.menu.clock_source.internal.build.f_cpu1t=32 MHz
328.menu.clock_source.internal.build.f_cpu1_=32000000L
328.menu.clock_source.internal.build.f_cpu2t=16 MHz
328.menu.clock_source.internal.build.f_cpu2_=16000000L
328.menu.clock_source.internal.build.f_cpu3t=8 MHz
328.menu.clock_source.internal.build.f_cpu3_=8000000L
328.menu.clock_source.internal.build.f_cpu4t=4 MHz
328.menu.clock_source.internal.build.f_cpu4_=4000000L
328.menu.clock_source.internal.build.f_cpu5t=2 MHz
328.menu.clock_source.internal.build.f_cpu5_=2000000L
328.menu.clock_source.internal.build.f_cpu6t=1 MHz
328.menu.clock_source.internal.build.f_cpu6_=1000000L
328.menu.clock_source.external1=External 32 MHz
328.menu.clock_source.external1.build.clock_source=2
328.menu.clock_source.external1.build.f_osc=32000000L
328.menu.clock_source.external1.build.f_cpu1t=32 MHz
328.menu.clock_source.external1.build.f_cpu1_=32000000L
328.menu.clock_source.external1.build.f_cpu2t=16 MHz
328.menu.clock_source.external1.build.f_cpu2_=16000000L
328.menu.clock_source.external1.build.f_cpu3t=8 MHz
328.menu.clock_source.external1.build.f_cpu3_=8000000L
328.menu.clock_source.external1.build.f_cpu4t=4 MHz
328.menu.clock_source.external1.build.f_cpu4_=4000000L
328.menu.clock_source.external1.build.f_cpu5t=2 MHz
328.menu.clock_source.external1.build.f_cpu5_=2000000L
328.menu.clock_source.external1.build.f_cpu6t=1 MHz
328.menu.clock_source.external1.build.f_cpu6_=1000000L
328.menu.clock_source.external2=External 16 MHz
328.menu.clock_source.external2.build.clock_source=2
328.menu.clock_source.external2.build.f_osc=16000000L
328.menu.clock_source.external2.build.f_cpu1t=16 MHz
328.menu.clock_source.external2.build.f_cpu1_=16000000L
328.menu.clock_source.external2.build.f_cpu2t=8 MHz
328.menu.clock_source.external2.build.f_cpu2_=8000000L
328.menu.clock_source.external2.build.f_cpu3t=4 MHz
328.menu.clock_source.external2.build.f_cpu3_=4000000L
328.menu.clock_source.external2.build.f_cpu4t=2 MHz
328.menu.clock_source.external2.build.f_cpu4_=2000000L
328.menu.clock_source.external2.build.f_cpu5t=1 MHz
328.menu.clock_source.external2.build.f_cpu5_=1000000L
328.menu.clock_source.external2.build.f_cpu6t=.5 MHz
328.menu.clock_source.external2.build.f_cpu6_=500000L
328.menu.clock_source.external3=External 12 MHz
328.menu.clock_source.external3.build.clock_source=2
328.menu.clock_source.external3.build.f_osc=12000000L
328.menu.clock_source.external3.build.f_cpu1t=12 MHz
328.menu.clock_source.external3.build.f_cpu1_=12000000L
328.menu.clock_source.external3.build.f_cpu2t=6 MHz
328.menu.clock_source.external3.build.f_cpu2_=6000000L
328.menu.clock_source.external3.build.f_cpu3t=3 MHz
328.menu.clock_source.external3.build.f_cpu3_=3000000L
328.menu.clock_source.external3.build.f_cpu4t=1.5 MHz
328.menu.clock_source.external3.build.f_cpu4_=1500000L
328.menu.clock_source.external3.build.f_cpu5t=750 kHz
328.menu.clock_source.external3.build.f_cpu5_=750000L
328.menu.clock_source.external3.build.f_cpu6t=375 kHz
328.menu.clock_source.external3.build.f_cpu6_=375000L

# Clock frequencies
#328.menu.clock.1={build.f_cpu1t}     <--- Dynamic menu not working.
328.menu.clock.1=1/1 clock source (Not for 328D internal)
328.menu.clock.1.build.f_cpu={build.f_cpu1_}
328.menu.clock.2=1/2 clock source
328.menu.clock.2.build.f_cpu={build.f_cpu2_}
328.menu.clock.4=1/4 clock source
328.menu.clock.4.build.f_cpu={build.f_cpu3_}
328.menu.clock.8=1/8 clock source
328.menu.clock.8.build.f_cpu={build.f_cpu4_}
328.menu.clock.16=1/16 clock source
328.menu.clock.16.build.f_cpu={build.f_cpu5_}
328.menu.clock.32=1/32 clock source
328.menu.clock.32.build.f_cpu={build.f_cpu6_}

[seisfeld]

Please keep the possibility to freely choose internal or external and up to 32Mhz on both options. We have custom designed hardware (with 32MHz crystal) with the 328 for which I originally contributed the possibility to pick the clock. We also have documentation with screenshots, so I'd prefer to not make it tooo complex to pick the clock if possible. I'd also keep it as generic as possible (i.e. not mention all the various board vendors - impossible to keep up to date!?).

[LaZsolt]

@seisfeld

Okay, I edited my suggestion.

[jg1uaa]

In fact, I have no idea to edit boards.txt because I couldn't conclude two point of views; chip-specific or board-specific. Chip-specific setting is the best to make flexibility maximum, I support it.

By the way, I am looking for adding configuration of 115200bps-bootloader(avrdude) setting. Many boards uses 57600bps except MassDuino. How should I put it?

[dwillmore]

How does the esp8266 do it? They have selectable upload speeds for their boards.

On Sat, Mar 13, 2021 at 7:57 PM SASANO Takayoshi @.***> wrote:

In fact, I have no idea to edit boards.txt because I couldn't conclude two point of views; chip-specific or board-specific. Chip-specific setting is the best to make flexibility maximum, I support it.

By the way, I am looking for adding configuration of 115200bps-bootloader(avrdude) setting. Many boards uses 57600bps except MassDuino. How should I put it?

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/dbuezas/lgt8fx/pull/119#issuecomment-798810164, or unsubscribe https://github.com/notifications/unsubscribe-auth/ACPEX7FUSVLIE5ISHV6HKBTTDQCYHANCNFSM4ZDXIQHA .

[pixelwaster]

@jg1uaa You don't need a special bootloader. I used Optiboot optiboot_lgt8f328p.hex and brother-yan's LGTISP. See issue #52 for the WAVGAT SWD, SWC, and RST header pins.

I believe that SuperUserNameMan has updated brother-yan's LGTISP but I have not had a chance to use it.

[LaZsolt]

Not tested, but what about this?

# Upload Speeds
328.menu.upload_speed.57600=57600
328.menu.upload_speed.57600.upload.speed=57600
328.menu.upload_speed.115200=115200
328.menu.upload_speed.115200.upload.speed=115200

[SuperUserNameMan]

Hey guys, if you're really willing to add support for external clocks as low as 375kHz, that might be cool that you add this support for internal clocks as well.

According to 328p and 328d datasheets, the clock prescaler CLKPR supports prescale values of 1,2,4,8,16,32,64,128 and 256. Which means that the internal clock speed can be set as low as 500 kHz, 250 kHz and 125 kHz.

[jg1uaa]

@pixelwaster issue #52 solved my problem, (this is off-topic) how to connect WAVGAT UNO R3's ICSP pins to SWDICE_mkII. thanks. @LaZsolt I leave boards.txt to you, please... @SuperUserNameMan whoa, I want to see under 1MHz world. Already this PR supports 1/64 - 1/256 prescaler settings.

[LaZsolt]

Hey guys, if you're really willing to add support for external clocks as low as 375kHz, that might be cool that you add this support for internal clocks as well.

375 kHz = external12 MHz divided by 32

[LaZsolt]

@jg1uaa

@LaZsolt I leave boards.txt to you, please...

Okay.

My first idea does not look nice:

I think it will better if I make more different boards for case of 16 MHz and 12 MHz external crystal in the boards.txt

[jg1uaa]

Previous idea was calculate F_DIV by F_CPU and F_OSC pair, but this is difficult to make a menu that @LaZsolt 's "1/n clock source". I rewrited boards.txt to give F_OSC and F_DIV. F_CPU is caluculated by F_OSC/F_DIV in platform.txt now.

[LaZsolt]

@jg1uaa

I rewrited boards.txt to give F_OSC and F_DIV. F_CPU is caluculated by F_OSC/F_DIV in platform.txt now.

No. In my opinion F_CPU macro won't calculate its value. I don't know it is acceptable syntax in all the libraryes, or not. Eg. with 32 MHz oscillator divided by 2 this modification will produce: F_CPU = 32000000L/2 instead of F_CPU = 16000000L

[jg1uaa]

@LaZsolt current boards.txt and platform.txt is a sample that can specify F_CPU by using F_OSC and F_DIV. I hope the parser (not compiler) will calculate F_OSC/F_DIV value and reduce the problem, but currently not. revert them? (except main.cpp)

[LaZsolt]

@jg1uaa

I rewrited boards.txt to give F_OSC and F_DIV. F_CPU is caluculated by F_OSC/F_DIV in platform.txt now.

I made a test on your calculated F_CPU. It is working absolutely perfect.

F_CPU = (32000000L/2) Last time I didn't notice the parentheses.

[LaZsolt]

I made 2 more menus for the boards with 16 and 12 MHz crystals and left unmodified the old board menu. After this modification the menu look like this:

[LaZsolt]

The boards.txt for that Menu above. (click)

[jg1uaa]

@LaZsolt

F_CPU = (32000000L/2) Last time I didn't notice the parentheses.

Even if the parentheses has added, I doubt they passed to compiler properly. So I wrote test code at https://github.com/jg1uaa/lgt8fx_clkinfo. At least current arduino-1.8.13 keeps '(' and ')' so I think there is no problem.

And. can I download your boards.txt and add to this PR?

[LaZsolt]

@jg1uaa

And can I download your boards.txt and add to this PR?

Of course you can download my boards.txt and add to this PR.

[jg1uaa]

@LaZsolt added, thanks!

[jg1uaa]

I reordered variant of boards.txt, LQFP32 first (previous: LQFP48 first). And, added 19200bps upload menu to support PR #126 by @youxiaojie

[youxiaojie]

1.dear, friend, I see the the datasheet, 328p and d both support 32.768k crystal, and I have a board leaving a pad, and seemly ready for a 32.768K crystal by size. and how to set this board?

ver 1.05 p20 LGT8FX8D 内部 OSC 振荡器可以工作在高频和低频两种模式下,用户需要根据外接晶振 的实际大小控制内部 OSC 振荡器工作在正确的模式下。同样内部的 RC 振荡器也分为高频和 低频两种。PMCR 寄存器的最低 4 位用于控制这四种时钟源。控制关系如下:

lgt328d internal osc can run in high frequency mode and low frency mod, to setting the register to insure internal osc work in suitable mod. the same to internal RC. the 4bit LSB does this: PMCR PMCR[0] 32M RC 1 enable 0 disable PMCR[1] 32K RC 1 enable 0 disable PMCR[2]400K ~ 20MHz OSC RC 1 enable 0 disable PMCR[3]32K ~ 400K OSC 1 enable 0 disable

LGT8FX8D 系统上电后,默认使用 32MHz RC 作为系统时钟源,内核工作在时钟源的 8 分 频(2MHz)。用户可以通过设置 PMCR 寄存器以及系统预分频寄存器(CLKPR)改变默认配置。 如果用户需要更改主时钟源配置,需要在切换时钟前保证切换后的时钟源处于稳定的工 作状态。因此需要在切换主时钟源之前,通过 PMCR[3:0]使能所需时钟源,并等待到时钟稳 定后才能进行切换。 lgt328 using 32M RC as default, core works at 32Mhz/8=4Mhz(? error on datasheet!),we can setting PMCR and CLKPR tomodify default. setting PMCR[3:0] to enable clock source, then after stable, PMCR[6:5] switch main clock source.

时钟源使能并等待稳定后,可以通过 PMCR[6:5]切换主时钟。其中 PMCR[5]用于选择是 内部 RC 振荡器和外部晶振,PMCR[6]用于选择高速时钟源和低速时钟源。

主时钟源选择: PMCR[6] PMCR[5] 主时钟源 0 0 内部 32MHz RC 振荡器(系统默认)internal hfrc default 0 1 外部 400K ~ 20MHz 高速晶振 external hfosc 1 0 内部 32KHz RC 振荡器 in'l rc 1 1 外部 32K ~ 400KHz 低速晶振 ex'l osc

So I want to ask here,does our lib can handle with pmcr[3:0]=1011 pmcr[6;5]=11?

and another question from 328p datasheet: (v105 p22) E2P_clk E2P_clk 时钟用于产生 FLASH 接口访问时序。E2P_clk 产生访问 E2PCTL 访问 FLASH 接口 的时序。(E2P_clk 固定来自内部 32MHz HFRC 振荡器的 32 分频(1MHz)。如果用户需要使 用 E2PCTL 模块读写内部程序 FLASH 或者数据 FLASH 空间,需要提前使能内部 32MHz 振 荡器。e2p_clk is fixed from in'l 32Mhz hfrc divided by 32,(32Mhz/32), we need to enable 32Mhz hfRC before using e2pctl model r/w in'l program space and data space,)

however 328d is not mention this.

therefor I thought the eeprom lib recently tested. If I using external osc, is it work correct? and therefor I ask this question: So I want to ask here,does our lib can handle with pmcr[3:0]=1011 pmcr[6;5]=11? it contains two meaning, one is about 32.768Khz crystal, the other is for compatible and safe, we enable and change to externel osc for accurate clock while keep int'l 32M RC and 32k RC enabled at the same time?

and bout CLKPR, is it suitable for ex'l crystal? no document how to set up when using ex'l crystal of 32.768khz. do you have interest to test it?

[LaZsolt]

@SuperUserNameMan: whoa, I want to see under 1MHz world. @youxiaojie

When I tried to compile a simple Blink under 1 MHz, then I got these message:

C:\Users\.....\1.0.6\cores\lgt8f\Arduino.h:111:44: warning: division by zero [-Wdiv-by-zero]
 #define clockCyclesToMicroseconds(a) ( (a) / clockCyclesPerMicrosecond() )

My recommendation is: Remove support all less than 1 MHz frequencies from boards.txt.

The Arduino evinronment is designed for 16 or 8 MHz, but working well at 4 Mhz too. Edit: But there are lot of functions (eg. delay()) not designed lower frequencies than 1 MHz, or even not designed such a frequencies which have fractional parts. (1.5 MHz , 11.0592 MHz , etc.)

[youxiaojie]

http://ruemohr.org/~ircjunk/avr/baudcalc/avrbaudcalc-1.0.8.php?postbitrate=115200&postclock=18.432 I ordered 18.432Mhz crystal to solder to the board, this is baud friendly speed, I will try!

[jg1uaa]

@LaZsolt should I remove 1.5MHz (with external 12MHz Xtal) support?

[LaZsolt]

@jg1uaa Yes you should remove 1.5 MHz support. :(

This calculation #define clockCyclesPerMicrosecond() ( F_CPU / 1000000L ) cause big timing erros in micros() , delay() , millis() , pulseIn(), etc

Edit: I think correcting timing errors at low frequencies and creating for documents is too big efforts for our little team.