Dan Smathers

Adding 2021/03/30 discussion (from meeting minutes) Current framework: load a test (binary), start a hart, hart runs, hart signals finished, extract results from memory to verify it ran correctly/check signature....

I was trying to match wording with AIA since it seems similar. from aia spec: "Registers eip0 through eip63 contain the pending bits for all implemented interrupt identities, and are...

https://github.com/riscv/sail-riscv/blob/master/model/riscv_sys_exceptions.sail /* xRET handling involves three functions: * * get_xret_target: used to read the value of the xret target (no control flow transfer) * set_xret_target: used to write a value...

adding [MarkHillHuawei](https://github.com/MarkHillHuawei) comment from merge of #276 here: My only comment is that for systems which only support horizontal traps (e.g. U/M with no N-extension and M only systems) then...

software doesn't need to set bits 0, 2, 4 because those bits are WPRI in xstatus. There is a post 1.0 proposal to have a different CLIC behavior based on...

I updated the revision history to state CSIP interrupt ID was changed from 12 to 16. leaving this issue open to discuss your second question. My understanding is that all...

copying [JamesKenneyImperas](https://github.com/JamesKenneyImperas) comment from commit to here and reopening this issue for easier tracking in TG meetings : This is a minor point, but I think it would help readability...

yes. that is the implication that all xinhv, xpil fields for all priv levels are zeroed when switching from **all** CLIC to **all** CLINT modes. For 1.0, we are only...

(reopening for better tracking) Can you spell out specifically what is different from what I've said here? I think I'm missing what you are getting at and want clarified. Maybe...

closed by #285