Panic entering unreachable code

[omarandlorraine]

I'm running into an unreachable! code here:

https://github.com/daniel5151/armv4t_emu/blob/7146935b514124f2ce5b1a911a81790c51b1e4c0/src/arm.rs#L447

From what I can see, this is during instruction decode, after figuring out the instruction is either HwSgnXferR or HwSgnXferI. Then, there's a match statement to determine if the opcode is "halfword load", "signed byte" or "signed half". The remaining option, and I can see the comment for this says "SWP", but I don't know what that means.

So is this a flaw in the instruction decoder somehow? Or is this related to my other issue?

[daniel5151]

Much like my other comment on #9, it's been a long time since I've paged-in the right context for this project, so I couldn't easily tell you if this was an "intentional" unreachable! or not.

If you think this is a bug, feel free to point out the relevant part(s) of the ARM spec / other work folks have done to clarify what you expect the behavior to be. I'm happy to review and merge any reasonable PRs sent my way.