danbone

lib-create creates verilog DPI wrapper with non-matching ports (ignores LSB index)

2

It appears that verilator is ignoring port LSB index when creating the SV wrapper file for the DPI library. My sv file test.sv: `module test ( input logic [7:4] a,...

TinyEMU had some support for networking/mounting devices to share data. Is this possible to do with Dromajo? If so any guides/advice on how to do it?

Cannot compile with Profile build type

9

I'm trying to compile with CMAKE_BUILD_TYPE=Profile but I'm getting the following error: ``` /home/dan/anaconda3/envs/sparta/bin/../lib/gcc/x86_64-conda-linux-gnu/12.3.0/../../../../x86_64-conda-linux-gnu/bin/ld: /home/dan/anaconda3/envs/sparta/bin/../x86_64-conda-linux-gnu/sysroot/usr/lib/../lib/gcrt1.o: relocation R_X86_64_32S against symbol `__libc_csu_fini' can not be used when making a PIE object; recompile...

Add L1 Instruction Cache

3

Adding an L1 Instruction Cache for fetch as noted in #143 - Updated fetch unit so that it requests a block of instructions per cycle from the instruction cache. The...

Add decoupled frontend (+ L1 Instruction Cache)

1

As the branch prediction API is coming to a close, I'd like to propose adding a decoupled frontend with an L1 instruction cache. I did cover some of this with...