Docs: better description of "the testbench interface"

[dan-fritchman]

Re:

    class Tb:
        # Seems to be a requirement of a 'Tb' to have a "single, scalar port".
        VSS = h.Port()

That fact, in contrast, looks like it could be more clear in the docs.

In short:

• Hdl21 does not "make up" signals for you, ever
• SPICE always has one "made up" one: global ground, AKA node zero
• Hence testbenches expose a single port, and vlsir.spice hooks it up to that global ground

Originally posted by @dan-fritchman in https://github.com/dan-fritchman/Hdl21/issues/176#issuecomment-1700280538