Port-Directions Elaborator Pass

[dan-fritchman]

Task: add an elaboration pass which checks for the directional validity of port-connections.

Each port has a four-value enumerated PortDir attribute direction:

class PortDir(Enum):
    """ Port-Direction Enumeration """

    INPUT = 0
    OUTPUT = 1
    INOUT = 2
    NONE = 3

References on the specific rules abound for Verilog, VHDL, Virtuoso, etc.
Hdl21 rules may require some combination of these (and some further debate) as:

• (a) Hdl21 targets (as a, if not primary goal) exporting to Verilog and similar signal-flow HDLs, but
• (b) Hdl21 modules target "analog-ier" circuits, which often have different (and looser) definitions of which directions "work together"

Example: current summing, as in a DAC. Specifying each unit-cell's output as PortDir.OUTPUT seems the highest designer-clarity. But wiring an array of such outputs together generally requires special handling for signal-flow languages such as Verilog.

There will likely be plenty of other similar trade-offs to be found.