Add ESD check for direct power connections to gates

[d-m-bailey]

Maybe allow a minimum resistance for power connections to gates.

The setting would be added to the model file where 0 ohm would be no check.

The check would only be for fixed gates (min=sim=max) to power.

Maybe flag any connection not equal to bulk/source net.

Power connections should be flagged for nmos and ground connections for pmos.