Add HWGen: Hardware code generator

[JerrymZhao]

Overview

This PR adds HWGen, a hardware code generator that extends CVXPYgen to generate Verilog for FPGA and ASIC implementations of convex optimization solvers.

Features

• Verilog code generation from CVXPY models
• Verilator integration
• Multiple parallelization architectures (parameter-level, solution-level, hybrid)
• Example implementations: codegen_pid, regression, MPC, power optimization

Structure

HWGen/
├── scripts/          # Code generation tools
├── regression/       # Example: linear regression
├── mpc_re/          # Example: model predictive control
├── power/           # Example: power optimization
└── README.md

Compatibility

• Non-invasive: does not modify existing CVXPYgen code
• Apache 2.0 licensed
• Works as standalone module alongside CVXPYgen's C generation

[maxschaller]

Thank you for this contribution!

[maxschaller]

I suggest to enable FPGA generation as

cpg.generate_code(problem, solver='explicit', solver_opts={'fpga': True})

Also, we need to think about how tests will look like.

[JerrymZhao]

Maybe not, right now I just copy and paste generated solver c code to the example project sub-folders for demonstration purposes. After that or with other data types support, I should change the workflow to follow yours.

On Wed, Oct 15, 2025 at 09:13 Maximilian Schaller @.***> wrote:

@.**** commented on this pull request.

In HWGen/README.md https://github.com/cvxgrp/cvxpygen/pull/94#discussion_r2430869520:

@@ -0,0 +1,245 @@ +# PDAQP Hardware Generator

+Automated RTL generation and verification for PDAQP controllers + +--- + +## Quick Start + +```bash +# Positional syntax +make complete my_project/pdaqp.c my_project/pdaqp.h

Will this command follow cpg.generate_code(problem, code_dir='my_project', solver='explicit')?

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[JerrymZhao]

Sure, I can change the generation command follow your suggestion.

On Wed, Oct 15, 2025 at 09:19 jingmin zhao @.***> wrote:

Maybe not, right now I just copy and paste generated solver c code to the example project sub-folders for demonstration purposes. After that or with other data types support, I should change the workflow to follow yours.

On Wed, Oct 15, 2025 at 09:13 Maximilian Schaller < @.***> wrote:

@.**** commented on this pull request.

In HWGen/README.md https://github.com/cvxgrp/cvxpygen/pull/94#discussion_r2430869520:

@@ -0,0 +1,245 @@ +# PDAQP Hardware Generator

+Automated RTL generation and verification for PDAQP controllers + +--- + +## Quick Start + +```bash +# Positional syntax +make complete my_project/pdaqp.c my_project/pdaqp.h

Will this command follow cpg.generate_code(problem, code_dir='my_project', solver='explicit')?

— Reply to this email directly, view it on GitHub https://github.com/cvxgrp/cvxpygen/pull/94#pullrequestreview-3338036338, or unsubscribe https://github.com/notifications/unsubscribe-auth/A4DPYIDFNJN4UV737NRDTGD3XWNTFAVCNFSM6AAAAACJALTEJOVHI2DSMVQWIX3LMV43YUDVNRWFEZLROVSXG5CSMV3GSZLXHMZTGMZYGAZTMMZTHA . You are receiving this because you authored the thread.Message ID: @.***>

[darnstrom]

Would it make sense to make the hardware generation available for pdaqp directly? To me it seems like the hardware generation works directly with information available from pdaqp. So the dependencies would be cvxpygen -> pdaqp -> hwgen instead of cvxpygen -> pdaqp and cvxpygen -> hwgen, which to me seems cleaner. Or are there some information used in the hardware generation that is only available in the cvxpygen problem and not in the multi-parameteric program that is available in pdaqp?