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Published 20 hours ago • verified publisher icon cvut

Recreate unitests for RISC-V

Open jdupak opened this issue 3 years ago • 3 comments

Modify the unit tests present in https://github.com/cvut/qtrvsim/tree/master/src/machine/tests to work with RISC-V.

  • Implement each tested component in separate file. See https://github.com/cvut/qtrvsim/blob/master/src/machine/execute/alu.test.h and https://github.com/cvut/qtrvsim/blob/master/src/machine/CMakeLists.txt:94.
  • Memory and cache should be OK, just move it.

jdupak avatar Nov 23 '21 22:11 jdupak

I have done the moving so now we just need to fix the changed tests. It is prepared in branch rv-tests.

  • [x] cache
  • [x] memory
  • [x] registers
  • [ ] instruction
  • [ ] program_loader
  • [x] core

jdupak avatar Dec 17 '21 20:12 jdupak

The all original complex core tests has been switched to RISC-V, see a9c15510cfad494dc98b9ab9e4ad7b3daddf63d3 and 043fbb17e3e91e08d03a3cfe8ef453ee4d40d846

ppisa avatar Mar 19 '22 11:03 ppisa

Memory tests re-enabled and extended b1f16dbbde2fe7d551f8500a341591d03e7f718d

ppisa avatar Jan 11 '23 22:01 ppisa