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How to use with verilog/systemVerilog?
Is your feature request related to a problem? Please describe. How to use with verilog/systemVerilog?
Describe the solution you'd like Appears not to function with .v and .sv files. Works with .c etc. A setting to work with other file type, or any text file by default.
Describe alternatives you've considered none.
Additional context Verilog basically has a syntax like c.
i will second this - we have a mostly SystemVerilog env with only some C++/C and we'd like to standardize on DoxyGen and having this work in VScode would be nice