Add support for SystemVerilog, and allow passing additional arguments to verilator

[asinghani]

Recently discovered this library and started integrating into my workflow and I've absolutely loved it, but noticed a few features that were lacking and added them in:

1. SystemVerilog support - The build function was hardcoded to only allow ".v" files, added ".sv" as well to allow for top-level files to be SystemVerilog (of which a sufficient subset is supported in Verilator that using SystemVerilog files with Verilator is not uncommon).

2. Allow parameter overrides - Some of my tests passed parameters into the top-level module to allow testing the module under different conditions, so build now takes a parameters dict object that is converted into -G flags and passed to verilator.

3. Allow passing additional custom arguments to verilator at build time.