creiter64
creiter64
The documentation in https://vunit.github.io/verification_components/user_guide.html mostly shows what's available, but not really how to use theses verification components. I have also found this example: https://github.com/VUnit/vunit/tree/master/examples/vhdl/axi_dma/src/test but it is only minimally documented.
Hi all, According to https://vunit.github.io/verification_components/vci.html#bus-master-vci VCI bus master components seem to provide overloads accepting both `std_logic_vector` addresses as well as `natural` type adresses. It would be very convenient to have...
Hi all, I have fusesoc setup to build my core, including a target to run testbenches via VUnit. My *.core file looks something like this: ``` CAPI=2: name: fancy::testcore:0.0.1 description:...
Hi all, I'm not 100% if that's how it's suposed to work, but I feel like it's not. If I declare an AXI bus master with this statement: ``` constant...
Hi all, It would be very helpful if VUnit had support for using `check_equal(...)` on the `ieee.fixed_pkg` data types. Currently I have to do all my testbenches using fixed point...
**Description** I have a VHDL2008 testbench with VUnit that includes a module from the Xilinx UNIMACR/UNISIM library. I managed to sucessfully compile the Xilinx libraries using the [script from the...
### Proposed new feature or change: In https://github.com/numpy/numpy/issues/13375 `is_integer()` got added to numpy float types, but it can not be applied on ndarrays of dtype=floating. I'd expect that the function...
**Describe the Issue** v1.4.1 and above cause an exception when connection to my camera. **To Reproduce** Execute the sample code **Sample Code** ```python from harvesters.core import Harvester from pathlib import...