Tim Crawford
Tim Crawford
Cause may not be the same, but this is going to become very apparent after the coreboot update. coreboot will issue a global reset after changing the IME mode to...
Looks like it's [`SpdProfileSelected`](https://github.com/intel/FSP/blob/6879b89ae02ad9079c6d7334e4d6a3dff15d649e/CometLakeFspBinPkg/CometLake1/Include/FspmUpd.h#L268-L273). This would be set in `romstage.c`, like how we already override `SaOcSupport` and `PrimaryDisplay`.
We should document the first boot after flashing takes longer due to memory training. Can you get it to happen and provide the output of cbmem? ``` cd coreboot/util/cbmem make...
Needs repro on latest release.
Yes. From what I remember, overclocking was disabled because we got reports of the system locking up/crashing with 3200 MHz RAM. - https://github.com/system76/coreboot/commit/6b23f22d59c25bca4a1192833c5b78ad989892d6
Timestamp doesn't matter because I cherry pick all the commits to a new base for the coreboot release updates. Here is the same commit from when we were on 4.16...
Screw sizes are listed in "Appendix A: Part Lists" of the Clevo service manuals. Unfortunately the tables are not searchable, but they seem to at least use the form "SCREW...
Should removing LXD be done separately? Have a release with VCS files ignored but still using LXD?
I will do it separately, since I'm unsure of how the PiHSM signing will work.
I'd expect to only see Unix epoch on System76 provided firmware and only if my logic for converting from a string to a timestamp is wrong. For LVFS provided firmware,...