William D. Jones

>You've mentioned that you want to avoid artifact mingling, but there isn't any in first place, any more than there is artifact mingling when you synthesize two different designs (using...

As for your other points: >It's not clear that there is a single "right way" to invoke sby. It has a lot of configuration options and those are not just...

>I propose we leave multiclock out of an initial implementation. Recently, I've been running into similar [problems](https://github.com/nmigen/nmigen/issues/526#issuecomment-723388086) with the SMT solver "holding the circuit in a single state to force...

>I'm not entirely sure why CXXRTL would be involved? Incomplete thought, not important. Meant to edit it out.

When I wrote this, I needed a way to get `amaranth` env variables to be available to the `ssh` session. The `~/.profile` dance was my attempt at a [portable](https://github.com/amaranth-lang/amaranth/pull/461#discussion_r463976353) way...

> The SSH executor could generate a script on the fly to do this, with the appropriate shebang line and then directly execute that file. The `.profile` dance allows to...

>I might be missing something, but I do not see how generating a setup script on the fly would not still provide this. I misunderstood your previous comments in multiple...

#596 will close this.

@RobertBaruch You may find [this](https://github.com/cr1901/yosys-experiments/tree/master/clk2fflogic/multiclk) helpful as to "how does the presence/lack of `multiclk` interact with a single/multiple clocks"? I don't know offhand if it helps with your specific problem,...

>I assume you have set HAS_FPU to false and LOG_LENGTH to 0? `LOG_LENGTH` was unmodified. Setting it helps a bit, but... ``` Info: Device utilisation: Info: TRELLIS_SLICE: 15430/12144 127% Info:...