Alec Edgington
Alec Edgington
Currently throws an exception with the message "Circuit has implicit wireswaps".
Disabled in #284 . Try to find a way to re-enable it, perhaps allowing this warning if necessary.
See https://github.com/CQCL/pytket/actions/runs/7148621469/job/19469840915 Perhaps due to a quimb update?
Several of the example notebooks ("entanglement swapping", "qiskit integration" and "ucc vqe") take a very long time to run (15 minutes or more). These are currently skipped by the `check-examples`...
When run on the CI, it seems that the `IBMQEmulatorBackend` initialization requires a `token` to be passed explicitly. This is what we do in the tests on the pytket-qiskit repo....
```python from pytket import Circuit from pytket.qasm import circuit_to_qasm_str from pytket.unit_id import BitRegister circuit = Circuit() areg = circuit.add_c_register(BitRegister("a", 1)) breg = circuit.add_c_register(BitRegister("b", 1)) circuit.add_c_not(arg_in=areg[0], arg_out=areg[0], condition=breg[0]) qasm = circuit_to_qasm_str(circuit,...
Adding their phases to the circuit's global `phase` parameter.
# Description Please summarise the changes. # Related issues Please mention any github issues addressed by this PR. # Checklist - [ ] I have performed a self-review of my...
#1201 reverted #941 because it caused some regressions in compilation. For example, with this circuit and sequence of passes: ```python import json from pytket.circuit import Circuit, OpType from pytket.passes import...