Difference with STM32F3xxx?

[rascafr]

Thanks the huge work. Works well with STM32F0 devices, but not with STM32F3xx, the assembly code is stuck into an infinite loop.

Tried to debug the code with OpenOCD, seems like the chip is blocked at the ilopend instruction.

Have you an idea about where the problem may come from? Is there such a huge difference between M0 and M3 assembly code instruction and how it works?

Regards

[cpldcpu]

Curious! No idea what the issue is. I have never tried it on CM3, but I believe others have. The CM3 is a superset of the CM0.

One potential issue, however, is that the timing becomes more unpredictable with higher clocked CM3 MCUs, since there will be flash waitstates. Could be worth trying to reduce the clockspeed.

Edit: One other thing: Have you checked for a register allocation issue?

[rascafr]

Wow, thanks a lot for the quick answer! :) I've changed the clockspeed of the STM32F303 (72MHz to 16MHz then 8MHz) but the problem is still here.

The assembly code seems to block in the bit 1 operation (08000d2c → 08000d34 → 08000d38 → 08000d40 → 08000d2c → etc.), here is a copy of the disassembly code during debug:

What do you mean by a register allocation issue? Register overridden?

Again, thanks a lot!

[cpldcpu]

It's most likely an issue with flash timing and code cache. The bitbanging approach is not very suitable for cores beyond CM0.