no SUBCKT if loading from verilog instead of GHDL

[nonchip]

I slightly modified one of the provided flows to replace the GHDL step with:

read_verilog -sv -formal ../main.sv ../vinclude/*.sv
hierarchy -check -top Mover
proc

but the generated spice will not contain any SUBCKTs, which PCBPlace dies about. any ideas?

the code at the time of writing this issue is available in this commit, executed from the sim/pcb/ folder with this command: yosys flow_discrete_LTL.ys