mini-rv32ima
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cnlohr
Please express true isa as RV32IMAZicsr_Zifencei
This is RV32IMAZicsr_Zifencei. you should also note that the atomics are non-atomic operations and are used for bit manipulation.
Base Integer Instruction Set, 32-bit | 40 Standard Extension for Integer Multiplication and Division | 8 Standard Extension for Atomic Instructions | 11 Control and Status Register (CSR) | 6 Instruction-Fetch Fence | 1
totaling in 66 instructions
Please be more specific about what is needed? Keep in mind this is a single-core hart + there is no memory ordering constraints as everything happens synchronously.
Do you have any tests I can test against?
I have considered also reducing functionality of A to AMOSwap only though I am unsure how to clarify this. Do you have any feedback? Considering A's SW will invalidate any other pending load operations, I don't see any harm in allowing all operations to pass synchronously. Maybe I'm misunderstanding something?
Please be more specific about what is needed? Keep in mind this is a single-core hart + there is no memory ordering constraints as everything happens synchronously.
Documentation. You should explain how the Zicsr and Zifencei extensions are also implemented and the caveats of the atomic extension being non-atomic.
Do you have any tests I can test against?
I have considered also reducing functionality of A to
AMOSwaponly though I am unsure how to clarify this. Do you have any feedback? Considering A's SW will invalidate any other pending load operations, I don't see any harm in allowing all operations to pass synchronously. Maybe I'm misunderstanding something?
There are none as there is only one CPU.
also idk if u know this but you can have GCC emulate multiplication and just omit the M extension. there is also an option in BR to do so.
I am aware of this, but it added to the complexity significantly for the targets where I could do that and I couldn't figure out how to build the kernel against RV32IA using buildroot.
I will need to do more research to really understand RV32A. I still don't actually understand how it works. It would be "nice" to make it actually atomic.
Tbh I'm impressed it works without it but nice to know it's not actually necessary in practice.
I mean I Would like to add proper support, at least for AMOSwap but I don't understand what to do based on the language used in the spec.
Go look at libgcc it's what implements multiplication when there is no hw multiplier. Look in the gcc root gcc/libgcc/config/riscv/atomic.c I think that emulates C atomics when HW doesn't support it. So I would take that as a reference.
Just add documentation of the caveats I explained. If you want to fix the caveats you can refer to my last post. Or just document them. You should also explained what you did with the fence and friends instructions.
What I'm trying to explain is I still don't understand how what I've done is different from how it should be. I can't really document what I don't understand.
I just reread the spec in that section again.
Would a good approach be to, inside the emulator, emulate the AMOs as other atomics. I.e. make them appear as LR.W/SC.W? It feels like that is easier to emulate than actual AMOs.
For the time being, I've added the following note:
†: Zifence+RV32A are stubbed. So, tweaks will need to be made if you want to emulate a multiprocessor system with this emulator.
What I'm trying to explain is I still don't understand how what I've done is different from how it should be. I can't really document what I don't understand.
That's fine I don't understand it well either. Just a general explanation that they are not to spec. Which you have done now!
If you want this will make Linux without M extension and also shortens both the defconfigs https://github.com/Mr-Bossman/buildroot/commits/mini
@Mr-Bossman how long does boot take? How big is your kernel image?
Ignore the file ext. 4MiB Image.zip
this / is in qemu in yours it takes ~0.3s for my PC.
