cnlohr
Incorrect gpio macros for x035 (possibly others)
Made a ticket for this as IDK when i'll be able to get to it, someone might before me
#if defined(CH32X03x)
#define funPinMode( pin, mode ) { *((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3)) = ( (*((&GpioOf(pin)->CFGLR)+((pin&0x8)>>3))) & (~(0xf<<(4*((pin)&0x7))))) | ((mode)<<(4*((pin)&0x7))); }
^ doesn't work with pins > 7
Also the GPIO_CFGLR_PIN_MODE_Typedef is incorrect.
Not only that but calling funPinMode to alternate between GPIO_CNF_OUT_PP and GPIO_CNF_IN_PUPD is not working properly, the bits in the CFGLR are not being cleared. This macro has to be reworked from the ground up, I'm working on a solution.
It turns out I've forgot to set GPIO_Speed_10MHz for input mode, if you don't set the working frequency it will not work properly sorry it was skill issue.
output: funPinMode( pin, GPIO_Speed_10MHz | GPIO_CNF_OUT_PP );
input: funPinMode( pin, GPIO_Speed_10MHz | GPIO_CNF_IN_PUPD );
GPIO has two configuration registers:
- GPIOx_CFGLR — responsible for pins 0..7
- GPIOx_CFGHR — responsible for pins 8..15
That is:
- If you have, for example,
PA4CFGLR is used, because it is < 7. - If you have
PA9then the configuration goes to CFGHR, and the formula is the same (4 bits per pin, only insideCFGHR).
Therefore, the macro GpioOf
*((&GpioOf(pin)->CFGLR) + ((pin & 0x8) >> 3))
selects the right register:
(pin & 0x8) >> 3= 0 for 0–7 CFGLR(pin & 0x8) >> 3= 1 for 8–15 CFGHR
So the logic is correct.
And by the way
funPinMode( pin, GPIO_Speed_10MHz | GPIO_CNF_OUT_PP );
is the same as
funPinMode( pin, GPIO_CFGLR_OUT_10Mhz_PP);
Here is a table for memory
| name | dec | hex | CNF | MODE |
|---|---|---|---|---|
| GPIO_CFGLR_IN_ANALOG | 0 | 0x0 | 00 | 00 |
| GPIO_CFGLR_IN_FLOAT | 4 | 0x4 | 01 | 00 |
| GPIO_CFGLR_IN_PUPD | 8 | 0x8 | 10 | 00 |
| GPIO_CFGLR_OUT_10Mhz_PP | 1 | 0x1 | 00 | 01 |
| GPIO_CFGLR_OUT_2Mhz_PP | 2 | 0x2 | 00 | 10 |
| GPIO_CFGLR_OUT_50Mhz_PP | 3 | 0x3 | 00 | 11 |
| GPIO_CFGLR_OUT_10Mhz_OD | 5 | 0x5 | 01 | 01 |
| GPIO_CFGLR_OUT_2Mhz_OD | 6 | 0x6 | 01 | 10 |
| GPIO_CFGLR_OUT_50Mhz_OD | 7 | 0x7 | 01 | 11 |
| GPIO_CFGLR_OUT_10Mhz_AF_PP | 9 | 0x9 | 10 | 01 |
| GPIO_CFGLR_OUT_2Mhz_AF_PP | 10 | 0xA | 10 | 10 |
| GPIO_CFGLR_OUT_50Mhz_AF_PP | 11 | 0xB | 10 | 11 |
| GPIO_CFGLR_OUT_10Mhz_AF_OD | 13 | 0xD | 11 | 01 |
| GPIO_CFGLR_OUT_2Mhz_AF_OD | 14 | 0xE | 11 | 10 |
| GPIO_CFGLR_OUT_50Mhz_AF_OD | 15 | 0xF | 11 | 11 |
