Allow `Wire`s to be instantiated from constants

[clvv]

Problem

Currently, there is no notion of constant wires in RCC traits. In AlgWire trait, we directly support operation of Wire against other constant values. This behavior is rather unintuitive and incurs additional hurdles for the circuit writer, because a constant is not a Wire.

Proposed solution:

In wire traits:

• Change the semantic of Wire so that it can hold a constant value.
• Remove operation of Wire against non-Wire values.

In each builder:

• implement Into<Wire> for intended constant values (u32, F, etc.)
• Builders will implement a Wire abstractly, not assuming that it consists of a single witness element. E.g. rcc-halo2 likely will need to change its Wire to an enum consisting of Witness or Constant.

Eventually, we should support "expression" builders that builds a circuit symbolically to enable optimization passes. This change should play nicely into enabling such "expression" circuit builder.