Need tests for Verilog integer type conversion behavior

[cbiffle]

There are subtleties to how fixed-width integral types like BitVector n get converted to and from Integer in Verilog. It's fairly easy to get wrong. See #219 and #222 .

We should have tests for this. It's currently kind of difficult to write reliable tests, because the issues arise only when operations like fromInteger# appear in an expression context. Small changes to the code can cause the compiler to either

1. Evaluate the entire fromInteger# expression to a literal integer, or
2. Assign the result of fromInteger# to a named net,

either of which will hide the behavior seen in #219.

We could test this more precisely by testing the backend in isolation from the rest of GHC, e.g. producing a test fixture Component, feeding that through the backend, and verifying the simulation behavior with iverilog. We currently have no tests that behave this way, so we'd need to extend the test suite.