`Clash.Backend.Verilog.modifier` ignores slices on non-BitVectors and produces wrong result type

[martijnbastiaan]

Crucially:

https://github.com/clash-lang/clash-compiler/blob/31857597f103a2a62eb8657a4b7c3360bfbe484c/clash-lib/src/Clash/Backend/Verilog.hs#L751

should read

    hty = BitVector (start-end+1)

Furthermore, it shouldn't match on BitVector:

https://github.com/clash-lang/clash-compiler/blob/31857597f103a2a62eb8657a4b7c3360bfbe484c/clash-lib/src/Clash/Backend/Verilog.hs#L748

as most things in Verilog are BitVectors anyway, so slicing is allowed.

[alex-mckenna]

We should appeal to the definition of what is scalar / vector in Verilog like @rowanG077 did in #2184, and make sure both point to some relevant source note about what is scalar / vector in Verilog

[martijnbastiaan]

While I'm fairly sure the - => + fix is correct, the other changes trigger CI failures in other parts. I've worked around it in my deconstructMaybe, so the PR can be merged. But it's still worth looking into at some point..

[leonschoorl]

Seems those CI failure are only in the VHDL tests