clare7

I am currently using `minion-v0.4` as well. However I have made some changes in `config.scala` in order to build a new `CONFIG` for simulation. The new `CONFIG` has the extension...

Ah ok. I have checked my coding and yeap I have accidentally messed with the `UseDebug` in the `LowriscvScala.scala` file. After amendment and re-run `./DebugConfig-sim +waitdebug` I manage to get...

Alright noted. One more concern, After run `./DebugConfig-sim +load=hello.riscv +waitdebug` on Terminal 1 (the program file is in the same directory as the simulator) `opensocdebugd tcp` on Terminal 2 ```...

And also, running the python script : `python runelf.py hello.riscv` gives me the following error: ``` Traceback (most recent call last): File "./executable/runelf.py", line 1, in import opensocdebug ImportError: No...

Hi I just checked. The first instruction is indeed on 0x4000_0000. I have also run CTM and STM and check the log files. Seems like the hello executable is running...

@wallento Oh you are right there. The path generated from the source set_env.sh is not pointing to the lib folder for python binding. Thanks! now the script works! as for...

Hi, The problem remained the same of which I am not able to solve yet. At the moment I just the STM and CTM for debugging and testing. But it...

Yes I want to have a 128-bit bus between LL2 and to DDR controller and the DDR controller has the support for 128-bit bus. Right now I am using v0.4

I have made necessary changes and the compilation seems alright. But I faced the followed error during testing: `/lowrisc-chip/src/test/cxx/common/dpi_ram_behav.cpp:180: bool Memory32::write(uint32_t, const uint32_t&, const uint32_t&): Assertion `(addr & 0x3) ==...

Yes the error jumpout at the beginning of the simulation. This happen only after I changed the bandwidth This is what I run on the command line: `TestMem-sim-debug +vcd +vcd_name=test.vcd...