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cjdrake
Sequential Logic
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seqlogic issues
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We need an equivalent for Verilog's `assume` / `assert`. Using [Ready/Valid Protocol Primer](https://cjdrake.substack.com/p/readyvalid-protocol-primer) as a starting point, for Tx/Rx implement the following checks: * `NeverReadyUnknown` (control signals cannot be X...
enhancement
- [ ] Reference Model (SoftFloat) - [ ] Test Suite (TestFloat) - [ ] Formats - [ ] `FNToRecFN` - [ ] `RecFNToFN` - [ ] `INToRecFN` - [...
enhancement