trex-core
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Why does a dest MAC is invalid ?
trex>start -f stl/udp_1pkt_mpls_bak.py
start - Port 1 dest MAC is invalid and there are streams without explicit dest MAC.
trex>
root@SixWind:/home/trex-core-master/scripts/stl# more udp_1pkt_mpls_bak.py from trex_stl_lib.api import * from scapy.contrib.mpls import * # import from contrib folder of scapy import argparse
class STLS1(object):
def __init__ (self):
pass;
def create_stream (self):
# 2 MPLS label the internal with s=1 (last one)
pkt = Ether()/MPLS(label=17,cos=1,s=0,ttl=255)/MPLS(label=12,cos=1,s=1,ttl=12)/IP(src="100.1.1.2",dst="100.1.1.1")/UDP(dport=12,sport=1025)/('x'*20)
# burst of 17 packets
return STLStream(packet = STLPktBuilder(pkt = pkt ,vm = []),
mode = STLTXSingleBurst( pps = 1, total_pkts = 17) )
def get_streams (self, tunables, **kwargs):
parser = argparse.ArgumentParser(description='Argparser for {}'.format(os.path.basename(__file__)),
formatter_class=argparse.ArgumentDefaultsHelpFormatter)
args = parser.parse_args(tunables)
# create 1 stream
return [ self.create_stream() ]
def register(): return STLS1()
root@SixWind:/home/trex-core-master/scripts/stl#
root@SixWind:/etc# more trex_cfg.yaml
- port_limit : 2 version : 2 #List of interfaces. Change to suit your setup. Use ./dpdk_setup_ports.py -s to see available options interfaces : ["0000:00:04.0","0000:00:05.0"] port_info : # Port IPs. Change to suit your needs. In case of loopback, you can leave as is. - ip : 100.1.1.2 default_gw : 100.1.1.1 - ip : 200.1.1.2 default_gw : 200.1.1.1
root@SixWind:/etc#
root@SixWind:/home/trex-core-master/scripts# sudo ./dpdk_setup_ports.py -s
Network devices using DPDK-compatible driver
0000:00:04.0 'Virtio network device' drv=uio_pci_generic unused=igb_uio,vfio-pci 0000:00:05.0 'Virtio network device' drv=uio_pci_generic unused=igb_uio,vfio-pci
Network devices using kernel driver
0000:00:03.0 'Virtio network device' if=mgmt0 drv=virtio-pci unused=igb_uio,vfio-pci,uio_pci_generic Active 0000:00:06.0 'Virtio network device' if=eth3 drv=virtio-pci unused=igb_uio,vfio-pci,uio_pci_generic
Other network devices
Try to check the post status, probably there is no arp resolve for the default_gw : 100.1.1.1 you can try to do this manually using arp resolve command. Another way is to set the destination MAC explicitly in the profile
see here https://trex-tgn.cisco.com/trex/doc/trex_stateless.html#_tutorial_source_and_destination_mac_addresses
thanks Hanoh
@hhaim I want to send traffic to the port at 100% rate, but now I see that the port rate is only 0.13%, what should I do?
trex>start -m 100% -f stl/udp_1pkt_mpls_bak.py
trex>stats Global Statistics
connection : localhost, Port 4501 total_tx_L2 : 207.33 Mbps ▼▼
version : STL @ v3.04 total_tx_L1 : 263.36 Mbps ▼▼
cpu_util. : 100.0% @ 1 cores (1 per dual port) total_rx : 0 bps
rx_cpu_util. : 0.0% / 0 pps total_pps : 350.21 Kpps ▼▼
async_util. : 0% / 5.82 bps drop_rate : 207.33 Mbps
total_cps. : 0 cps queue_full : 1,155,005,236 pkts
Port Statistics
port | 0
-----------+------------------
owner | root
link | UP
state | TRANSMITTING
speed | 200 Gb/s
CPU util. | 100.0%
-- |
Tx bps L2 | ▼▼ 207.33 Mbps
Tx bps L1 | ▼▼ 263.36 Mbps
Tx pps | ▼▼ 350.21 Kpps
Line Util. | 0.13 %
--- |
Rx bps | 0 bps
Rx pps | 0 pps
---- |
opackets | 530308168
ipackets | 365
obytes | 39242804432
ibytes | 92476
tx-pkts | 530.31 Mpkts
rx-pkts | 365 pkts
tx-bytes | 39.24 GB
rx-bytes | 92.48 KB
----- |
oerrors | 0
ierrors | 0
trex>
root@SixWind:/home/trex-core-master/scripts/stl# cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 6 model name : QEMU Virtual CPU version 2.5+ stepping : 3 microcode : 0x1 cpu MHz : 2194.842 cache size : 16384 KB physical id : 0 siblings : 1 core id : 0 cpu cores : 1 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pse36 clflush mmx fxsr sse sse2 syscall nx lm rep_good nopl xtopology cpuid pni cx16 x2apic hypervisor lahf_lm cpuid_fault pti bugs : cpu_meltdown spectre_v1 spectre_v2 bogomips : 4389.68 clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management:
processor : 1 vendor_id : GenuineIntel cpu family : 6 model : 6 model name : QEMU Virtual CPU version 2.5+ stepping : 3 microcode : 0x1 cpu MHz : 2194.842 cache size : 16384 KB physical id : 1 siblings : 1 core id : 0 cpu cores : 1 apicid : 1 initial apicid : 1 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pse36 clflush mmx fxsr sse sse2 syscall nx lm rep_good nopl xtopology cpuid pni cx16 x2apic hypervisor lahf_lm cpuid_fault pti bugs : cpu_meltdown spectre_v1 spectre_v2 bogomips : 4389.68 clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management:
processor : 2 vendor_id : GenuineIntel cpu family : 6 model : 6 model name : QEMU Virtual CPU version 2.5+ stepping : 3 microcode : 0x1 cpu MHz : 2194.842 cache size : 16384 KB physical id : 2 siblings : 1 core id : 0 cpu cores : 1 apicid : 2 initial apicid : 2 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pse36 clflush mmx fxsr sse sse2 syscall nx lm rep_good nopl xtopology cpuid pni cx16 x2apic hypervisor lahf_lm cpuid_fault pti bugs : cpu_meltdown spectre_v1 spectre_v2 bogomips : 4389.68 clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management:
processor : 3 vendor_id : GenuineIntel cpu family : 6 model : 6 model name : QEMU Virtual CPU version 2.5+ stepping : 3 microcode : 0x1 cpu MHz : 2194.842 cache size : 16384 KB physical id : 3 siblings : 1 core id : 0 cpu cores : 1 apicid : 3 initial apicid : 3 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pse36 clflush mmx fxsr sse sse2 syscall nx lm rep_good nopl xtopology cpuid pni cx16 x2apic hypervisor lahf_lm cpuid_fault pti bugs : cpu_meltdown spectre_v1 spectre_v2 bogomips : 4389.68 clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management:
root@SixWind:/home/trex-core-master/scripts/stl#