Is it possible to get good power performance and area (PPA) estimates before place and route (PnR)?

[cirosantilli]

After synthesis, before PnR.

Hopefully only with a cell library, but without the full fab design rules.

https://electronics.stackexchange.com/questions/364422/how-to-find-power-delay-and-area-of-a-synthesized-design-using-design-compiler says yes, so how accurate are those?

https://www.quora.com/unanswered/Is-it-possible-to-get-good-power-performance-and-area-PPA-estimates-before-place-and-route-PnR