Chris Leary

`dslx_jit_wrapper` needs to anonymous namespace ir_text to avoid ODR violations?

1

Noticed the source files all have `ir_text[]` in the xls namespace -- even though it's `constexpr char char ir_text[]` still can cause ODR violations I presume (and these I imagine...

Right now they're tied together in a single tool invocation (`codegen_main` spits out a scheduling proto as a byproduct in its run) but they are separable, and it can be...

With the soon-to-land attribute grammar you cannot write: `uN[128]::MAX`, you must make a type alias and take `::MAX` on that, e.g. `type MyU128 = uN[128]; MyU128::MAX`. (Of course for all...

Generate packed arrays via VAST codegen

4

Currently we use unpacked arrays, which end up generating lots of unrolled assignments for propagating the array values around. Mark is working on switching us to packed arrays. I believe...

[enhancement] User-specified `dead_if(predicate)` akin to `assume(predicate)` to enable clock gating

1

### What's hard to do? (limit 100 words) Related to #542 -- similar to an "assume(p)" which would conceptually forward-propagate the truth of predicate `p` for subsequent optimization, for clock...

### What's hard to do? (limit 100 words) See https://doc.rust-lang.org/book/ch18-03-pattern-syntax.html#destructuring-structs It'd be nice to pattern match structs similar to record-style pattern matching in ML family of languages, Rust does it...

### What's hard to do? (limit 100 words) We noticed there are sometimes literals that are there for unclear reasons, e.g. literal.3 here: ``` top proc __test_module__P_0_next(__token: token, __state: bits[32],...

### What's hard to do? (limit 100 words) With #1050 we'll add the ability to have a locally scoped typedef for a proc, but that binding can't be referred to...

[dslx][cleanup] procs are not represented with explicit AST nodes

1

Functions get flattened against the top level of the DSLX module and tagged -- it'd be a higher fidelity representation to encapsulate functions within a proc AST node, so we...

### What's hard to do? (limit 100 words) Right now `fail!`/`assert!` in the DSL only become assert ops in the IR that turn into Verilog/SV assertions. On some chips there...