Christopher Batten
Christopher Batten
Ah ... ok ... that is not a hierarchical reference so ignore what I said above .... looks ok to me ... we would need to see a minimal failing...
Oh man .. not sure about that code at all ... FYI, at least in my group, we have moved away from en/rdy and back to val/rdy ... I wonder...
At least internally I have started using the pymtl4.0-dev branch. The whole send/recv thing with en/rdy was a bit of an experiment ... but ultimately I ended up going back...
Hmm ... is it possible to provide a minimal test case that illustrates the issue along with what the desired VCD output should be? @jsn1993 any thoughts on this issue?
Thanks! We will try to find time to take a look ...
Hmmm ... "const" is on the keyword list here: - https://github.com/pymtl/pymtl3/blob/master/pymtl3/passes/backends/verilog/util/utility.py#L112 So I think we would catch if you name a signal `const` but maybe we don't check field names?
Would make a great fix for a pull request if you are interested!
Right ... I think our point was we currently have a list of verilog keywords that get checked at translation although currently it looks like we don't check if bitstruct...
I think we write some specific metadata into a comment in the generated verilog so when we regenerate the verilog with different metadata it ends up forcing a recompile? Maybe...
hmmm ... what would the ideal Verilog be though? Should we turn clog2 into `$clog2` in the Verilog?